a number of processor structures are a tremendous category of parallel structures. through the years, numerous architectures were proposed to construct such platforms to fulfill the necessities of excessive functionality computing. those architectures span a wide selection of process forms. on the low finish of the spectrum, we will construct a small, shared-memory parallel approach with tens of processors. those platforms as a rule use a bus to interconnect the processors and reminiscence. Such platforms, for instance, have gotten average in high-performance graph­ ics workstations. those structures are referred to as uniform reminiscence entry (UMA) multiprocessors simply because they supply uniform entry of reminiscence to all professional­ cessors. those structures supply a unmarried tackle house, that's most well-liked by means of programmers. This structure, in spite of the fact that, can't be prolonged even to medium structures with enormous quantities of processors as a result of bus bandwidth barriers. To scale structures to medium diversity i. e. , to hundreds and hundreds of processors, non-bus interconnection networks were proposed. those structures, for instance, use a multistage dynamic interconnection community. Such platforms additionally offer worldwide, shared reminiscence just like the UMA structures. in spite of the fact that, they introduce neighborhood and distant stories, which result in non-uniform reminiscence entry (NUMA) structure. Distributed-memory structure is used for platforms with millions of professional­ cessors. those platforms range from the shared-memory architectures in that there's no globally obtainable shared reminiscence. as an alternative, they use message go­ ing to facilitate verbal exchange one of the processors. hence, they don't supply unmarried deal with space.